p r e l i m i n a r y t e c h n i c a l d a t a functional block diagram a dsp microcomputer ADSP-2187L features performance 25 ns instruction cycle time @ 3.3 volts, 40 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 400 cycle recovery from power-down condition low power dissipation in idle mode integration adsp-2100 family code compatible, with instruction set extensions 160k bytes of on-chip ram, configured as 32k words on-chip program memory ram and 32k words on-chip data memory ram dual purpose program memory for both instruction and data storage independent alu, multiplier/accumulator, and barrel shifter computational units two independent data address generators powerful program sequencer provides zero overhead looping conditional instruction execution programmable 16-bit interval timer with prescaler 100-lead tqfp system interface 16-bit internal dma port for high speed access to on-chip memory (mode selectable) 4 mbyte memory interface for storage of data tables and program overlays (mode selectable) 8-bit dma to byte memory for transparent program and data memory transfers (mode selectable) i/o memory interface with 2048 locations supports parallel peripherals (mode selectable) programmable memory strobe and separate i/o memory space permits glueless system design programmable wait state generation two double-buffered serial ports with companding hardware and automatic data buffering automatic booting of on-chip program memory from byte-wide external memory, e.g., eprom, or through internal dma port six external interrupts 13 programmable flag pins provide flexible system signaling rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. *ice-port is a trademark of analog devices, inc. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 uart emulation through software sport reconfiguration ice-port? emulator interface supports debugging in final systems general note this data sheet represents preliminary (x- grade) specifications for the ADSP-2187L 3.3v processor. general description the ADSP-2187L is a single-chip microcomputer optimized for digital signal processing (dsp) and other high speed numeric processing applications. the ADSP-2187L combines the adsp-2100 family base archi- tecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. the ADSP-2187L integrates 160k bytes of on-chip memory configured as 32k words (24-bit) of program ram, and 32k words (16-bit) of data ram. power down circuitry is also pro- vided to meet the low power needs of battery operated portable equipment. the ADSP-2187L is available in 100-lead tqfp package. in addition, the ADSP-2187L supports new instructions, which include bit manipulationsbit set, bit clear, bit toggle, bit test new alu constants, new multiplication instruction (x squared), biased rounding, result free alu operations, i/o memory trans- fers, and global interrupt masking, for increased flexibility. fabricated in a high speed, low power, cmos process, the ADSP-2187L operates with a 25 ns instruction cycle time. ev- ery instruction can execute in a single processor cycle. serial ports sport 1 sport 0 memory programmable i/o and flags byte dma controller 16k 3 24 pm 8k 3 24 overlay 1 8k 3 24 overlay 2 timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data external data bus external address bus internal dma port external data bus or full memory mode host mode 16k 3 24 pm 8k 3 16 overlay 1 8k 3 16 overlay 2
rev. 0 ADSP-2187L C2C p r e l i m i n a r y t e c h n i c a l d a t a the ADSP-2187Ls flexible architecture and comprehensive in- struction set allow the processor to perform multiple operations in parallel. in one processor cycle the ADSP-2187L can: ? generate the next program address ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computational operation this takes place while the processor continues to: ? receive and transmit data through the two serial ports ? receive and/or transmit data through the internal dma port ? receive and/or transmit data through the byte dma port ? decrement timer development system the adsp-2100 family development software, a complete set of tools for software and hardware system development, sup- ports the ADSP-2187L. the system builder provides a high level method for defining the architecture of systems under de- velopment. the assembler has an algebraic syntax that is easy to program and debug. the linker combines object files into an executable file. the simulator provides an interactive instruc- tion-level simulation with a reconfigurable user interface to dis- play different portions of the hardware environment. a prom splitter generates prom programmer compatible files. the c compiler, based on the free software foundations gnu c compiler, generates ADSP-2187L assembly source code. the source code debugger allows programs to be cor- rected in the c environment. the runtime library includes over 100 ansi-standard mathematical and dsp-specific functions. the ez-kit lite is a hardware/software kit offering a complete development environment for the entire adsp-21xx family: an adsp-218x based evaluation board with pc monitor software plus assembler, linker, simulator, and prom splitter soft- ware. the adsp-218x ez-kit lite is a low cost, easy to use hardware platform on which you can quickly get started with your dsp software design. the ez-kit lite includes the fol- lowing features: ? 33 mhz adsp-218x ? full 16-bit stereo audio i/o with ad1847 soundport ? codec ? rs-232 interface to pc with windows 3.1 control software ? ez-ice ? connector for emulator control ? dsp demo programs the adsp-218x ez-ice ? emulator aids in the hardware de- bugging of ADSP-2187L system. the emulator consists of hard- ware, host computer resident software and the target board connector. the ADSP-2187L integrates on-chip emulation sup- port with a 14-pin ice-port interface. this interface provides a simpler target board connection requiring fewer mechanical clearance considerations than other adsp-2100 family ez-ices. the ADSP-2187L device need not be rem oved from the target system when using the ez-ice, nor are any adapters needed. due to the small footprint of the ez-ice conne ctor, emu- lation can be supported in final board designs. the ez-ice performs a full range of functions, including: ? in-target operation ? up to 20 breakpoints ? single-step or full-speed operation ? registers and memory values can be examined and altered ? pc upload and download functions ? instruction-level emulation of program booting and execution ? complete assembly and disassembly of instructions ? c source-level debugging see designing an ez-ice-compatible target system in the adsp-2100 family ez-tools manual (adsp-2181 sections) as well as the designing an ez-ice compatible system section of this data sheet for the exact specifications of the ez-ice tar- get board connector. additional information this data sheet provides a general overview of ADSP-2187L functionality. for additional information on the architecture and instruction set of the processor, refer to the adsp-2100 family users manual . for more information about the development tools, refer to the adsp-2100 family development tools data sheet. architecture overview the ADSP-2187L instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single pro- cessor cycle. the ADSP-2187L assembly language uses an alge- braic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. serial ports sport 1 sport 0 memory programmable i/o and flags byte dma controller 16k 3 24 pm 8k 3 24 overlay 1 8k 3 24 overlay 2 timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data external data bus external address bus internal dma port external data bus or full memory mode host mode 16k 3 24 pm 8k 3 16 overlay 1 8k 3 16 overlay 2 figure 1. functional block diagram figure 1 is an overall block diagram of the ADSP-2187L. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provi- sions to support multiprecision computations. the alu per- forms a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arith- metic shifts, normalization, denormalization and derive expo- nent operations. the s hifter can be used to efficiently implement numeric for- mat control including multiword and block floating-point representations. *ez-ice and soundport are registered trademarks of analog devices, inc.
ADSP-2187L C3C rev. 0 p r e l i m i n a r y t e c h n i c a l d a t a the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computa- tional units. the sequencer supports conditional jumps, subroutine calls and returns in a single cycle. with internal loop counters and loop stacks, the ADSP-2187L executes looped code with zero over- head; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and pro- gram memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four pos- sible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for cir- cular buffers. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permit- ting the ADSP-2187L to fetch two operands in a single cycle, one from program memory and one from data memory. the ADSP-2187L can fetch an operand from program memory and the next instruction in the same cycle. in lieu of the address and data bus for external memory connec- tion, the ADSP-2187L may be configured for 16-bit internal dma port (idma port) connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct access to the dsps on-chip program and data ram. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with program- mable wait state generation. external devices can gain control of external buses with bus request/grant signals ( br , bgh , and bg ). one execution mode (go mode) allows the ADSP-2187L to con- tinue running from on-chip memory. normal execution mode re- quires the processor to halt while buses are granted. the ADSP-2187L can respond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level- sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchro- nous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the ADSP-2187L provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, there are eight flags that are programmable as inputs or outputs and three flags that are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) is decremented every n pro- cessor cycles, where n is a scaling value stored in an 8-bit regis- ter (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the ADSP-2187L incorporates two complete synchronous se- rial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the ADSP-2187L sports. for additional information on serial ports, refer to the adsp-2100 family users manual . ? sports are bidirectional and have a separate, double- buffered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and trans- mit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulse widths and timings. ? sports support serial data word lengths from 3 to 16 bits and provide optional a-law and m -law companding according to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique in- terrupts on completing a data word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated after a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, se- rial bitstream. ? sport1 can be configured to have two external interrupts ( irq0 and irq1 ) and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration. pin descriptions the ADSP-2187L will be available in a 100-lead tqfp pack- age. in order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. the external bus pins are configured during reset only, while serial port pins are software configurable during program execution. flag and interrupt functionality is re- tained concurrently on multiplexed pins. in cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
rev. 0 ADSP-2187L C4C p r e l i m i n a r y t e c h n i c a l d a t a common-mode pin descriptions pin # of input/ name(s) pins output function reset 1 i processor reset input br 1 i bus request input bg 1 o bus grant output bgh 1 o bus grant hung output dms 1 o data memory select output pms 1 o program memory select output ioms 1 o memory select output bms 1 o byte memory select output cms 1 o combined memory select output rd 1 o memory read enable output wr 1 o memory write enable output irq2 / 1 i edge- or level-sensitive inter rupt request 1 pf7 i/o programmable i/o pin irql0 / 1 i level -sensitive inte rrupt req uests 1 pf6 i/o programmable i/o pin irql1 / 1 i level-sensitive interrupt requests 1 pf5 i/o programmable i/o pin irqe / 1 i edge-sensitive interrupt requests 1 pf4 i/o programmable i/o pin mode d/ 1 i mode select inputchecked only during reset pf3 i/o programmable i/o pin during normal operation mode c/ 1 i mode select inputchecked only during reset pf2 i/o programmable i/o pin during normal operation mode b/ 1 i mode select inputchecked only during reset pf1 i/o programmable i/o pin during normal operation mode a/ 1 i mode select inputchecked only during reset] pf0 i/o programmable i/o pin during normal operation clkin, xtal 2 i clock or quartz crystal input clkout 1 o processor clock output sport0 5 i/o serial port i/o pins sport1 5 i/o serial port i/o pins irq1:0 edge- or level-sensit ive i nterrupts, fi, fo flag in, flag out 2 pwd 1 i power-down control input pwdack 1 o power-down control output fl0, fl1, fl2 3 o output flags vdd and gnd 16 i power and ground ez-port 9 i/o for emulation use notes 1 interrupt/flag pins retain both functions concurrently. if imask is set to en- able the corresponding interrupts, then the dsp will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2 sport configuration determined by the dsp system control register. soft- ware configurable. memory interface pins the ADSP-2187L processor can be used in one of two modes, full memory mode, which allows bdma operation with full external overlay memory and i/o capability, or host mode, which allows idma operation with limited external addressing capabilities. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the processor is running. full memory mode pins (mode c = 0) pin # of input/ name(s) pins output function a13:0 14 o address output pins for program, data, byte and i/o spaces d23:0 24 i/o data i/o pins for program, data, byte and i/o spaces (8 msbs are also used as byte memory addresses) host mode pins (mode c = 1) pin # of input/ name(s) pins output function iad15:0 16 i/o idma port address/data bus a0 1 o address pin for external i/o, pro- gram, data, or byte access d23:8 16 i/o data i/o pins for program, data byte and i/o spaces iwr 1 i idma write enable ird 1 i idma read enable ial 1 i idma address latch pin is 1 i idma select iack 1 o idma port acknowledge configur- able in mode d; open drain in host mode, external peripheral addresses can be decoded using the a0, cms , pms , dm s, and ioms signals interrupts the interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. the ADSP-2187L provides four dedicated external interrupt in- put pins, irq2 , irql0 , irql1 and irqe . in addition, sport1 may be reconfigured for irq0 , irq1 , flag_in and flag_out, for a total of six external interrupts. the adsp- 2187l also supports internal interrupts from the timer, the byte dma port, the two serial ports, software and the power-down control circuit. the interrupt levels are internally prioritized and individually maskable (except power down and reset). the irq2 , irq0 and irq1 input pins can be programmed to be either level- or edge-sensitive. irql0 and irql1 are level- sensitive and irqe is edge sensitive. the priorities and vector addresses of all interrupts are shown in table i.
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